Photoelectric conversion device and manufacturing mehtod therefor

ABSTRACT

A microfabricated device having a high vertical aspect ratio and electrical isolation between a structure region and a circuit region. The device may be fabricated on a single substrate and may include electrical interconnections between the structure region and the circuit region. The device includes a substrate and an isolation trench surrounding a structure region in the substrate. The isolation trench includes a lining of a dielectric insulative material. A plurality of microstructure elements are located in the structure region and are laterally anchored to the isolation trench.

STATEMENT OF GOVERNMENT RIGHTS

[0001] This invention was made with Government support under Grant(Contract) Nos. DABT63-93-C-0065 and DABT63-95C-0028 awarded by DARPA.The Government has certain rights to this invention.

BACKGROUND OF THE INVENTION

[0002] The present invention relates generally to microfabricateddevices, and more particularly to three dimensional microfabricateddevices having a high vertical aspect ratio.

[0003] Microelectromechanical systems (MEMS) integrate micromechanicalstructures and microelectronic circuits on the same silicon chip tocreate an integrated device. MEMS have many useful applications such asmicrosensors and microactuators. An example of a microsensor is agyroscope used in a missile guidance system. An example of amicroactuator is a micropositioner used to move a read/write head in adisk drive.

[0004] In surface micromachining, the device is fabricated by depositinga thin film on a surface. The thin film is typically deposited bychemical vapor deposition (CVD) and etched to yield a desired shape.Then a layer of sacrificial material underlying the thin film may beetched to open up passageways or clearances between moving parts of themicrostructure. The height of the microstructure is limited to thethickness of the deposited thin film. Since the thin film structure hasmicroscopic thickness, on the order of one micron, it tends to beflexible out of the plane of fabrication.

[0005] In view of the foregoing, there is a need for a way to maketaller microstructures (on the order of 10 to 250 microns). In addition,to increase the overlapping surface area of interdigited electrodes, themicrostructures should have a high vertical aspect ratio; that is, suchmicrostructures should have a height significantly larger than theirlateral width. Furthermore, to minimize the clearance betweeninterdigited electrodes, the channel between the interdigited electrodesshould also have a high vertical aspect ratio.

[0006] Several techniques have been developed for making high aspectratio microstructures, but these techniques have significant fabricationdifficulties. One problem in some existing techniques is that thestructural elements need to be wire bonded to the electronics. Becausedifferential capacitance-based sensors may require the interconnectionof many alternating positive and negative electrode plates (e.g., onehundred plates in an angular accelerometer), the large number of wirebonds makes this fabrication technique impractical.

[0007] Another problem in some existing techniques is difficulty inelectrically isolating the microstructure elements from each other andfrom the microelectronic circuits on the chip. Unless the electrodeplates are electrically isolated, the two sides of each sensingcapacitor will be shorted together through the substrate. Consequently,capacitive sensing schemes cannot be implemented easily using existingtechniques.

[0008] Accordingly, it would be useful to provide a microfabricateddevice in which the micromechanical structures have a high verticalaspect ratio and are electrically isolated from each other and from themicroelectronic circuits on the chip.

SUMMARY OF THE INVENTION

[0009] In one aspect, the invention is directed to a method offabricating a microelectromechanical system. The method includesproviding a substrate having a device layer, etching a first trench inthe device layer, depositing a dielectric isolation layer in the firsttrench, and etching a second trench in the device layer. The firsttrench surrounds a first region of the substrate, and the second trenchis located in the first region and defines a microstructure.

[0010] Implementations of the invention include the following. Circuitrymay be formed in a second region of the substrate outside the firstregion, and an electrical connection may be formed over the first trenchto connect the microstructure to the circuitry. The isolation layer mayfill the first trench, or a filler material may be deposited over theisolation layer in the first trench. The substrate may include a handlelayer, a sacrificial layer and the device layer. A portion of thesacrificial layer may be removed to release the microstructure. Thesacrificial layer may include silicon dioxide, the device layer mayincludes epitaxial silicon, and the isolation layer may include siliconnitride.

[0011] In another aspect, the invention is directed to a microfabricateddevice. The device includes a substrate having a device layer and anisolation trench extending through the device layer and surrounding afirst region of the substrate. The isolation trench includes a lining ofa dielectric insulative material. A plurality of microstructure elementsformed from the device layer are located in the first region and arelaterally anchored to the isolation trench.

[0012] Implementations of the invention include the following. Thelining may fill the isolation trench, or a filler material may bedeposited on the lining and fill the trench. Circuitry may be formed ina second region of the substrate outside the first region, and anelectrical connection may be disposed over the isolation trench toconnect at least one of the microstructure elements to the circuitry.The substrate may include a handle layer, a sacrificial layer and thedevice layer. A portion of the sacrificial layer may be removed from thefirst region to form a gap between the microstructure elements and thehandle layer. The sacrificial layer may include silicon dioxide, thedevice layer may include epitaxial silicon, and the lining may includesilicon nitride.

[0013] Advantages of the invention include the following. Themicrostructures are electrically isolated from the microelectroniccircuits, but can be electrically connected to the microelectroniccircuits by interconnect layers. The device may be fabricated utilizingstandard microfabrication techniques. The invention is compatible withexisting very large scale integrated (VLSI) circuit fabricationprocesses so that microelectronic circuits may be fabricated on thesurface of the device. The microstructures have a high vertical aspectratio (on the order of 10:1 to 25:1 or even higher). Microsensorsfabricated according the invention have a larger sense capacitance, andthus an increased signal-to-noise ratio, due to the increased surfacearea between the electrode fingers. The microstructures also have alarger mass and a larger moment of inertia, and consequently thermalnoise is reduced. In addition, the high vertical aspect ratiomicrostructures have a large separation of vibrational modes.

[0014] Other advantages and features of the invention will becomeapparent from the following description, including the claims anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a schematic top plan view of a microfabricated device inaccordance to the present invention.

[0016]FIG. 2 is a cross-sectional view of the device of FIG. 1 alonglines 2-2.

[0017]FIG. 3 is an enlarged and perspective view of the microfabricateddevice of FIG. 1.

[0018] FIGS. 4, 6-11, 13 and 15 are schematic cross-sectional views.

[0019]FIGS. 5, 12 and 14 are schematic plan views illustrating steps inthe fabrication of the microfabricated device of FIG. 1. In addition,FIGS. 6, 13 and 15 are cross-sectional views of FIGS. 5, 12 and 14,respectively, along lines 6-6, 13-13 and 15-15, respectively. The scalein the plan views is not the same as the scale in the cross-sectionalviews.

[0020]FIG. 16A is a schematic cross-sectional view illustrating a dryrelease step for the fabrication process of the present invention.

[0021]FIG. 16B is a schematic cross-sectional view illustrating anisolation trench which is entirely filled by the isolation layer.

[0022]FIG. 17 is a scanning electron microscope photograph of amicrofabricated device fabricated in accordance with the presentinvention.

[0023]FIG. 18 is a scanning electron microscope photograph of across-section of an isolation trench.

[0024] FIGS. 19-25 are scanning electron microscope photographs ofdevices fabricated in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025]FIGS. 1, 2 and 3 illustrate a microfabricated device 10 inaccordance with the present invention. The illustrated microfabricateddevice is a linear accelerometer. However, the principles of theinvention are applicable to many other devices, such as vibromotors,angular accelerometers, gyroscopes, resonators, microactuators,microvalves, filters, and chemical detectors.

[0026] Device 10 includes a circuit region 12 and a structure region 14formed in a substrate 16. As will be described in more detail below,microstructure elements in structure region 14 are electrically isolatedfrom each other and from circuit region 12 by a filled isolation trenchregion 18.

[0027] A recess 20 is etched into an upper surface of substrate 16 instructure region. Recess 20 contains the various microstructureelements, such as electrodes fingers and plates, flexures, and proofmass beams or bodies, required by device 10. The microstructure elementsin recess 20 are defined and separated by a channel 28. At least some ofthe microstructure elements are separated from a handle layer 44 and canmove. In addition, because all of the microstructure elements arefabricated from a single device layer 48, the elements are coplanar.

[0028] Device 10 includes a proof mass 24 which is laterally anchored tosidewalls 22 of recess 20 by flexures 26. Flexures 26 are designed tosuspend proof mass 24 in recess 20 and to permit proof mass 24 tovibrate along the X-axis parallel to the surface of substrate 16. Aplurality of stationary electrode fingers 30 a and 30 b are anchored toand project inwardly along the Y-axis from sidewalls 23 of recess 20. Aplurality of movable electrode fingers 32 project from proof mass 24along the Y-axis and are interdigitated with stationary electrodefingers 30 a and 30 b. Each movable electrode finger 32 is adjacent toone stationary electrode finger 30 a and one stationary electrode finger30 b. The movable microstructure elements in structure region 14,including proof mass 24, electrode fingers 32 and flexures 26, areseparated from the bottom of recess 20 by an air gap 34. The air gap 34may have a width D which is defined by the thickness of a sacrificiallayer 46 between device layer 48 and handle layer 44.

[0029] Flexures 26 may have a width W_(F) of about two to six microns.Electrode fingers 30 a, 30 b and 32 may have a length L of about ten tofive-hundred microns and a width WE of about two to six microns.Stationary electrode fingers 30 a and 30 b may be separated from movableelectrode fingers 32 by a gap having a width W_(g) of about one to threemicrons.

[0030] The microstructure elements in structure region 14 have athickness T (see FIG. 2). The thickness T may be about ten microns toone-hundred microns, with the preferred thickness being determined bythe application and desired sensitivity. Even thicker microstructuresmay be possible as anisotropic etching technology improves. Thethickness T is much larger than the width W_(F) of flexures 26, thewidth W_(F) of electrode fingers 30 a, 30 b and 32, or the width W_(g)of the gap between the stationary and moveable electrode fingers.

[0031] Flexures 26 may have a vertical aspect ratio (a ratio of T toW_(F)) of at least about 10:1. Similarly, electrode fingers 30 a, 30 band 32 may have a vertical aspect ratio (the ratio of T to W_(g)) of atleast 5:1. The gap between stationary electrode fingers 30 a and 30 band movable electrode fingers 32 may have a vertical aspect ratio (theratio of T to W_(G)) of at least 10:1. Vertical aspect ratios of 25:1may be achieved utilizing current etching techniques.

[0032] The high vertical aspect ratio provides an increased surface areabetween the electrode fingers, and thus a larger sense capacitance. Theincreased sense capacitance provides an increased signal-to-noise ratio.In addition, the microstructures also have a larger mass and a largermoment of inertia, and consequently reduced thermal noise.

[0033] Furthermore, the thicker structures are more rigid in thevertical direction and thus less likely to move out of the plane offabrication. In addition, the high vertical aspect ratio microstructureshave a large separation of vibrational modes due to the significantdifference in rigidity of the microstructures in different directions.

[0034] Circuit region 12 contains the necessary integrated circuitry todrive and/or sense the position of proof mass 24. Circuit region 12 isnot shown in detail because its circuitry will depend upon the purposeof the device; that is, the circuitry will depend upon whether thedevice is an angular accelerometer, gyroscope, linear accelerometer,microactuator, etc. The microelectronic circuitry may be constructedaccording to known circuit designs, and thus the content of circuitregion 12 is not crucial to the invention. However, it may be noted thatcircuit region 12 may be fabricated utilizing traditional VLSIprocesses, such as complementary metal oxide semiconductor (CMOS)processes. As shown in FIG. 2, if circuit region 12 is fabricated usingCMOS processes, it may include both n-channel transistors 80 andp-channel transistors 82 (not shown in FIG. 1 for the reasons discussedabove).

[0035] The microstructure elements in structure region 14 may beelectrically connected to circuit region 12 by conductive electricalinterconnections 36 which extend over isolation trench 18. Theelectrical interconnections 36 may be formed of polysilicon or a metalsuch as aluminum, copper or tungsten.

[0036] The isolation trench 18 separates circuit region 12 fromstructure region 14. Isolation trench 18 preforms three primaryfunctions. First, isolation trench 18 electrically isolates structureregion 14 from circuit region 12. In addition, isolation trench 18electrically isolates the microstructure elements in structure region 14from each other. For example, because they project from differentportions of the isolation trench, stationary electrodes 30 a areelectrically isolated from stationary electrodes 30 b and from proofmass 24. Second, isolation trench 18 provides a lateral anchoring pointfor mechanically anchoring the microstructure elements in structureregion 14 to substrate 16. Third, isolation trench 18 provides a bridgeto support electrical interconnections 36 between the microstructureelements and the circuit region.

[0037] Isolation trench 18 extends entirely through the thickness ofdevice layer 48. Isolation trench 18 may have a width W_(T) of about twoto seven microns. Isolation trench 18 is lined with an isolation layer64. The isolation layer is an insulating dielectric, such as 0.5 micronsof silicon nitride. Isolation trench 18 may be back-filled with a fillermaterial such as undoped polysilicon. Alternately, isolation trench 18may be entirely filled by isolation layer 64, without use of a fillermaterial. Isolation layer 64 may provide the sidewalls 22 of recess 20.

[0038] Fabrication of device 10 comprises three basic steps: formationof isolation trench 18, formation of circuit region 12 and electricalinterconnections 36 by VLSI processing, and formation of structureregion 14.

[0039] Referring to FIG. 4, the fabrication process begins with theformation of isolation trench 18 in substrate 16. Substrate 16 includesa handle layer 44, a sacrificial layer 46, and a device layer 48. Thehandle layer 44 may comprise a material which bonds to sacrificial layer46. Handle layer 44 may be silicon or another high-temperaturesubstrate, such as quartz. Sacrificial layer 46 may be a layer ofsilicon oxide. Sacrificial layer 46 may have a thickness of betweenabout 0.5 and 2.0 microns, such as 1.0 microns.

[0040] Device layer 48 may include a surface sublayer 50 and anunderlying sublayer 52. Surface sublayer 50 is a layer of asemiconductor material suitable for VLSI processing. Surface sublayer 50may be formed of epitaxial silicon. Alternatively, surface sublayer 50may be composed of another semiconductor material such as galliumarsenide. Surface sublayer 50 may be about five microns thick. Thedopant levels in surface sublayer 50 may be selected to match a standardVLSI process. For example, surface sublayer 50 may be lightly doped withan n-type dopant for compatibility with a CMOS fabrication process.

[0041] Underlying sublayer 52 may be a semiconductor or other materialonto which surface sublayer 50 may be grown by an epitaxial process. Forexample, underlying sublayer 52 may be a single-crystal silicon<100>-substrate. Underlying sublayer 52 may be doped to independentlycontrol the electrical properties of the device, such as the resistivityof the microstructure elements in structure region 14. It isadvantageous to use antimony as a dopant in underlying sublayer 52because it minimizes diffusion of the dopant into surface sublayer 50.Underlying sublayer 52 may be about forty-five micron thick.

[0042] The thickness of device layer 48 will determine the totalthickness T of the microstructure elements in structure region 14. Thethickness of sacrificial layer 46 will determine the distance D betweenthe microstructure elements and handle layer 44.

[0043] Referring to FIGS. 5 and 6, an etch stop or pad oxide layer 54 isnext deposited on an upper surface of surface sublayer 50. Etch stoplayer 54 may be composed of an oxide, such as silicon dioxide, and maybe deposited by thermal oxidation. Etch stop layer 54 may have athickness of about 0.18 microns and may be formed on surface sublayer 50using a wet thermal oxidation step at about 900° C. for about fiftyminutes.

[0044] Still referring to FIGS. 5 and 6, etch stop layer 54 isphotolithographically defined, and both etch stop layer 54 and devicelayer 48 are etched to form a trench 60. The trench may have a widthW_(T) of about two to seven microns, and a depth equal to the totalthickness of device layer 48 and etch stop layer 54, i.e., aboutforty-five microns. The etch of etch stop layer 54 may be performedusing a deep anisotropic plasma etch. Specifically, the etch of the etchstop layer may be performed using reactive ion etching (RIE) by flowingthe gasses carbon tetraflouride (CF₄), trifluromethane (CHF₃) and helium(He) at 90 sccm, 30 sccm and 120 sccm, respectively. This etch may beperformed at a power of 850 watts and a pressure of 2.8 Torr.

[0045] The device layer 48 may be patterned etched. This etch may beperformed using an inductively coupled plasma (ICP) etch. The so-called“Bosch” process may be used, as this process currently providesstate-of-the-art anisotropic silicon etching. ICP etching services maybe obtained from the Microelectronics Center of North Carolina (MCNC) inResearch Triangle Park, North Carolina, or from the Center forIntegrated Systems of Stanford University in Palo Alto, Calif.

[0046] Referring to the top view of FIG. 5, trench 60 surrounds theportion of device layer 48 which will become structure region 14.Although shown as a simple rectangle, trench 60 may have a morecomplicated shape, and multiple trenches may be formed in the substrate.

[0047] Next, referring to FIG. 7, an isolation layer 64 is depositedonto substrate 16. Isolation layer 64 covers etch stop layer 54 andlines sidewalls 62 and floor 63 of trench 60 (see FIG. 5). The isolationlayer 64 is a conformal insulative dielectric, such as silicon nitride.Alternately, isolation layer 64 may be a thermal oxide. Isolation layer64 may be about 0.26 microns thick. A silicon nitride layer may bedeposited using low-pressure chemical vapor deposition (LPCVD) with thedeposition gasses dichlorosilane (SiH₂Cl₂) and ammonia (NH₃) at flowrates of 100 sccm and 25 sccm, respectively. The deposition may beperformed at a pressure of 140 mTorr and a temperature of 835° C.

[0048] Still referring to FIG. 7, a filler material 66 may be depositedto backfill trench 60. Filler material 66 is also deposited on isolationlayer 64. Filler material 66 may be an insulator, semiconductor orconductor. The filler material 66 may be undoped polysilicon and may bedeposited by CVD using silane (SiH₄) at a pressure of 375 mTorr at atemperature of 610° C. for about ten hours. The thickness of fillermaterial 66 is a function of the width of trench 60. For example, for anLPCVD process, the thickness of the layer of filler material is at leastone-half the width of the trench.

[0049] Referring to FIG. 8, a chemical mechanical polishing (CMP)process is then used to remove filler material 66 from the surface ofisolation layer 64. The filler material 66 is polished until it si flushwith the top surface of isolation layer 64.

[0050] Referring to FIG. 9, assuming that isolation layer 64 is composedof silicon nitride, a self-aligned nitride etch is performed next.First, a capping layer 68 is grown on filler material 66. Capping layer68 may be a thermal oxide which grows on the polysilicon of fillermaterial 66 but not on the nitride of isolation layer 64. Capping layer68 may be 0.24 microns thick and may be grown by a wet oxidation processat 900° C. for about two hours.

[0051] After depositing capping layer 68, the portion of isolation layer64 above etch stop layer 54 is removed. The portion of isolation layer64 lining trench 60 is not removed. Again assuming that isolation layer64 is silicon nitride, a blanket plasma nitrite etch is used to removeisolation layer 64. Underlying etch stop layer 54 and capping layer 68serve as etch stops. The blanket plasma nitride etch may be performedwith sulfur hexaflouride (SF₆) and helium (He) at flow rates of 175 sccmand 50 sccm, respectively. The etch may be performed at a pressure of375 mTorr and a power of 250 watts.

[0052] This completes the formation of isolation trench 18. Thedielectric material of isolation layer 64 lining the walls of trench 18electrically isolates structure region 14 from circuit region 12.Substrate 16 may now be subjected to standard VLSI processes to formcircuit region 12.

[0053] Referring to FIG. 10, capping layer 68 and etch stop layer 54 areremoved to expose the epitaxial silicon of surface sublayer 50. The etchmay be performed using a plasma etch with the etching gasses CF₄, CHF₃and He at flow 1:5 rates of 30 sccm, 35 sccm and 100 sccm, respectively.The etch may be performed at a power of 700 watts and a pressure of 3.0Torr.

[0054] Assuming that circuit region 12 is to be formed on an epitaxiallayer using a CMOS process, surface sublayer 50 is doped in circuitregion 12 to form an n-well 40 and a pwell 42. However, when n-well 40is formed, the portion of surface sublayer 50 in structure region 14 isalso subjected to the same n-type doping steps used in the circuitfabrication. This causes surface sublayer 50 in structure region 14 tobecome more conductive. This ensures that the entire thickness of devicelayer 48 in structure region 14 is a composed of a conductive material.

[0055] Next, referring to FIG. 11, transistors 80 and 82 are formed onsubstrate 16 using standard VLSI techniques to deposit gate structure86.

[0056] Then, referring to FIGS. 12 and 13, electrical interconnections36 are formed between the microstructure elements in structure region 14and circuit region 12. Electrical interconnections 84 are also formedbetween transistors 80 and 82 in circuit region 12. Electricalinterconnections 36 may be formed as part of the same standard VLSIprocess that deposits electrical interconnections 84. Each electricalinterconnection 36 includes a conductive layer 74 and an insulativelayer 70 to isolate device layer 48 from conductive layer 74. Insulativelayer 70 may be formed of silicon nitride. Such a layer may be 0.3microns thick and may be deposited by LPCVD with the deposition gassesSiH₂Cl₂ and NH₃, at flow rates of 100 sccm and 25 sccm, respectively.The deposition may be performed at a pressure of 140 mTorr and atemperature of 835° C. Insulative layer 70 may be patterned to formthrough-holes 72 where electrical contact between device layer 48 andconductive layer 74 is desired.

[0057] Following the deposition and patterning of insulative layer 70,conductive layer 74 is deposited and patterned to form the electricalinterconnections between structure region 14 and circuit region 12. Theconductive layer 74 extends over isolation trench 18 so that electricalinterconnections 36 provide the only connections between structureregion 14 and circuit region 12.

[0058] Conductive layer 74 may be a 0.54 micron thick layer of dopedpolysilicon deposited by LPCVD using the deposition gasses SiH₄ andphosphene (PH₃) at flow rates of 100 sccm and 1 sccm, respectively. Thedeposition may be performed at a temperature of 375 mTorr and atemperature of 610° C. for about five hours. Alternately, conductivelayer 74 may be composed of a metal such as aluminum, copper ortungsten.

[0059] Having formed the integrated circuitry in circuit region 12,device 10 may be completed by forming the microstructure elements instructure region 14. Referring to FIGS. 14 and 15, a second etching stepis used to etch trenches or channels 28 in structure region 14 of devicelayer 48. FIG. 15 shows the pattern that will be etched into devicelayer 48 to form channels 28 in phantom. Channels 28 may be etched usingan ICP etch similar to the etching step used to form trench 60. The etchstops at the buried sacrificial layer 46.

[0060] Finally, sacrificial layer 46 is etched to form air gap 34 andrelease proof mass 24 and flexures 26 from underlying handle layer 44.The release etch step may remove the sacrificial layer from beneathstationary electrode fingers 30 a and 30 b and may partially undercutisolation trench 18. The release etch may be performed using a timedhydrofluoric acid (HF) etch. This wet etch may be performed using about49% concentration HF for about one minute. The wet etch may be followedby critical point carbon dioxide drying.

[0061] The lithographic definition of channels 28 may 2 overlapisolation trench 18. This guarantees that all MEMS structures areelectrically isolated from one another even in the event of maskmisalignment by insuring the removal of all conductive material ofdevice layer 48 from the trench side walls. This may cause the etch ofchannels 28 to also etch a portion of filler material 66 in isolationtrench 18. As shown in FIG. 17, if filler material 66 is etched, thisprocess will create silicon nitride walls which bridge the gaps betweenthe adjacent electrode fingers.

[0062] In an alternate embodiment, a dry release process may be used toremove the portion of sacrificial layer 46 beneath structure region 14.Referring to FIG. 16A, the portion of handle layer 44 beneath structureregion 14 may be etched to form a cavity 90 and expose sacrificial layer46. The etching of handle layer 44 may be performed using an anisotropicwet etch with potassium hydroxide (KOH) or EDP. Alternately, handlelayer 44 could be isotropically etched. Then, sacrificial layer 46 maybe removed using a dry oxide etch through the cavity. In the resultingdevice, the microstructure elements in structure region 14 are suspendedin an open space rather than forming an air gap with handle layer 44.The dry release step permits the isolation layer 64 to be a thermaloxide layer rather than a nitride layer.

[0063] Referring to FIG. 16B, in another embodiment, trench 60 isentirely filled by isolation layer 64. This embodiment does not use afiller material 66. Instead, isolation layer 64 grows on the sidewallsof the trench to fill the trench. In this embodiment, trench 60 has awidth WT of only about one to two microns. No CMP step and no cappinglayer are needed in this embodiment because the isolation layer coversthe entire surface of sublayer 50.

[0064] In another embodiment, trench 60 could be etched throughsacrificial layer 46 to expose handling layer 44. Then isolation layer64 could be deposited onto sidewalls 62 and handle layer 44 at thebottom of trench 60. This would prevent the wet etch of the release stepfrom undercutting isolation trench 18 because the isolation trench wouldextend entirely to the bottom surface of handle layer 44.

[0065] Referring to FIG. 17, a device having an isolation trench wasfabricated. The trench electrically isolates adjacent stationaryelectrodes from each other and from the circuit region. A siliconnitride isolation layer lines the edges of the isolation trench, and itis filled with an undoped polysilicon filler material. A portion of thefiller material in the isolation trench was also etched, leaving siliconnitride walls bridging the gaps between the adjacent electrode fingers.

[0066] Referring to FIG. 18, the dark region at the bottom of the imageis the silicon oxide sacrificial layer and the grey region above it isthe silicon device layer.

[0067] The two vertical stripes are the silicon nitride isolationmaterial, and the rough region between the vertical stripes is thepolysilicon filler material. The region where the vertical stripes ofthe isolation layer curve and become horizontal show that the bottom ofthe isolation trench included a “footing effect”. That is, the bottom ofthe trench, and the isolation layer deposited therein, extendshorizontally into the device layer. It is believed that 1:5 this footingeffect is caused by lateral etching when the trench etch frontencounters the oxide of the sacrificial layer. The footing providesadditional mechanical strength to the anchors. In addition, as shown bythe black triangular region near the bottom of the trench, a “keyhole”is present where the polysilicon backfill did not completely close offthe bottom of the trench.

[0068] FIGS. 19-25 show a variety of test structures that werefabricated to evaluate the present invention. These test structuresincluded isolation trenches and interconnect layers to demonstrateprocess functionality. They did not include microelectronic circuits.The devices are a Z-axis gyroscope (FIG. 19), an angular accelerometer(FIG. 20), a linear accelerometer (FIG. 21), a resonant accelerometer(FIG. 22), a resonator (FIG. 23), a vibro-motor (FIG. 24), and astain-failure test device (FIG. 25).

[0069] In summary, a microfabrication process has been described forforming a device having a high vertical aspect ratio and electricalisolation between a structure region and a circuit region. The devicemay be fabricated on a single substrate and may include electricalinterconnections between the structure region and the circuit region.

[0070] The present invention has been described in terms of a preferredembodiment. The invention however is not limited to the embodimentdepicted and described. Rather the scope of the invention is defined bythe pending claims.

What is claimed is:
 1. A method of fabricating a microelectromechanicalsystem, comprising: providing a substrate having a device layer; etchinga first trench in the device layer, the first trench surrounding a firstregion of the substrate; depositing a dielectric isolation layer in thefirst trench; and etching a second trench in the device layer, the 10second trench located in the first region and defining a microstructure.2. The method of claim 1 further comprising forming circuitry in asecond region of the substrate outside the first region.
 3. The methodof claim 2 further comprising depositing an electrical connection overthe first trench to connect the microstructure to the circuitry.
 4. Themethod of claim 1 further comprising depositing a filler material overthe isolation layer in the first trench.
 5. The method of claim 1wherein the isolation layer fills the first trench.
 6. The method ofclaim 1 wherein the substrate further includes a handle layer and asacrificial layer.
 7. The method of claim 6 wherein the method furthercomprises removing a portion of the sacrificial layer to release themicrostructure.
 8. The method of claim 7 wherein the step of etching thefirst trench etches through the device layer to expose the sacrificiallayer.
 9. The method of claim 7 wherein the step of etching the secondtrench etches through the device layer to expose the sacrificial layer.10. The method of claim 6 wherein the sacrificial layer includes silicondioxide.
 11. The method of claim 1 wherein the device layer includesepitaxial silicon.
 12. The method of claim 1 wherein the isolation layerincludes silicon nitride.
 13. A microfabricated device, comprising: asubstrate having a device layer; an isolation trench extending throughthe device layer and surrounding a first region of the substrate, theisolation trench including a lining of a dielectric insulative material;and a plurality of microstructure elements formed from the device layerin the first region and laterally anchored to the isolation trench. 14.The device of claim 13 wherein the isolation trench further includes afiller material deposited on the lining and filling the trench.
 15. Thedevice of claim 13 wherein the lining fills the trench.
 16. The deviceof claim 13 further comprising circuitry formed in a second region ofthe substrate outside the first region.
 17. The device of claim 16further comprising an electrical connection disposed over the isolationtrench to connect at least one of the microstructure elements to thecircuitry.
 18. The device of claim 13 wherein the substrate furtherincludes a handle layer and a sacrificial layer.
 19. The device of claim18 wherein the sacrificial layer includes silicon dioxide.
 20. Thedevice of claim 18 wherein at least a portion of the sacrificial layeris removed from the first region to form a gap between themicrostructure elements and the handle layer.
 21. The method of claim 13wherein the device layer includes epitaxial silicon.
 22. The method ofclaim 13 wherein the lining includes silicon nitride.